The present invention relates to a read only semiconductor memory device, and more particularly to a read only memory device used in a memory device constituting a CMOS gate array fabricated using the master slice approach.
In general, gate array LSIs are used as circuitry having an intermediate character between microcomputers which obtain various functions utilizing software and custom made LSIs based on hard specification of users.
Such gate array LSIs can obtain desired hardware functions by interconnecting several hundred to thousand of gate circuit blocks provided on a chip in advance on the basis of the users' specification, and they are ordinarily fabricated in accordance with the master slice approach to vary the wiring pattern between unit cells in the wiring area according to the kind of the products so as to meet users' design specification.
Meanwhile, among recently available gate array LSIs, there are many ones such that gates are contiguously arranged also in wiring areas which have been provided between gate columns in the art to form a structure of the type comprising gates on the entire source, which is generally referred to as SOG (Sea of Gate), thereby improving the element density to assemble memory units as arbitrary positions. In this instance, the logic of the gates is realized by ROM (Read Only Memory) device.
FIG. 1 is a circuit diagram illustrating one example of an essential part of a ROM of the OR type used in a conventional read only semiconductor memory device. As seen from this figure, source grounded n-channel transistors Q11, Q12, Q13, Q21, . . . , Q23, and Q31 to Q33 are arranged in a matrix manner. This ROM circuit is provided with word lines WL1, WL2, and WL3 commonly connected to gates of transistors of the same columns, respectively, and bit lines BL1, BL2 and BL3 commonly connected to drains of transistors of the same rows, respectively. To these bit lines BL1, BL2 and BL3, drains precharging p-channel transistors Q1, Q2 and Q3 are connected, respectively wherein their gates are commonly connected to a precharge circuit 1 and their sources are connected to a drain supply voltage V.sub.DD (which will be simply call "V.sub.DD " hereinafter). Their drains of these transistors Q11, Q22 and Q33 are separated from the bit lines BL1, BL2 and BL3, respectively.
In this circuit, one first activate the precharge circuit 1 by a clock signal to place each bit line in a high (H) level. In this condition, when a word line selection is made, a transistor connected to the bit line is turned on, with the result that the concerned bit line is pulled down to low (L) level. However, such a pulldown does not occur in the transistor in which the drain and the bit line are separated from each other. As a result, a memory output appears on the bit line. Accordingly, this circuit can be called the circuit of the synchronous type, giving rise to the problem in use that it is required to precisely adjust the clock for precharge and the timing of an input address signal for selection of the word line.
FIG. 2 is a circuit diagram illustrating a conventional ROM circuit of the ratio type configured so that bit lines are always respectively pulled up by resistors R1, R2 and R3 instead of the precharge circuit and the p-channel transistors shown in FIG. 1. This circuit is of the asynchronous type because the bit lines are always pulled up independent of the selection of the word lines, resulting in no problem in the timing. However, this circuit has the shortcoming that a large d.c. current flows every time the address changes, resulting in large power dissipation.
FIG. 3 is a circuit diagram illustrating a further conventional ROM circuit used in the gate array in the prior art. This circuit is characterized in that the transistors Q11, Q22 and Q33 for producing a predetermined output are arranged so that their sources are connected to V.sub.DD instead of separation between the drains and the bit lines as in the prior art, thus providing a ROM of the asynchronous type and having a low power dissipation.
Because an output is small in this circuit, there is employed a circuit arrangement to pass each output through a p-channel transistor having a source connected to V.sub.DD and a compensation (sense-up) circuit comprising two stages of inverters, thereby allowing a slow rising of the potential on the bit line after selection of the word line to be changed into a quick and steep rising on the output line as shown in FIG. 4.
However, with such a compensation circuit, when the threshold voltage V.sub.TH of the n-channel transistor shifts to an upper voltage and that of the p-channel transistor shifts to a lower voltage due to the variation at the time of fabrication, the circuit threshold voltage V.sub.TH of the inverter becomes high. Accordingly, in the event that the H level on the bit line pulled up by the n-channel transistor of which source is connected to V.sub.DD by the selection of the word line is lowered by the circuit V.sub.TH of the inverter, there is a possibility that this circuit does not normally operate. Namely, the drawback with this circuit is that the range of the threshold voltage V.sub.TH is limited, resulting in small margin in the production and poor mass-productivity.
In addition, since the memory elements are constituted using only n-channel transistors in the above-mentioned three ROM circuits, the drawback with these circuits is that the p-channel transistor is not used in the COMS gate array, resulting in low element utilization factor.